Analysis On NOx Formation Of Biofuels

This paper proposes on analysis of NOx formation of biofuels by using Corn Oil Methyl Ester (COME) and Palm Oil Methyl Ester (POME). The main contribution of this work is to study and analyse NOx emission from biodiesel, which can improve biodiesel content and component in order to reduce NOx formation coming from Compression Ignition (CI) engine. This is achieved by using alkaline base catalyst transesterification process to convert from palm and corn oil, containing low Free Fatty Acid (FFA), to biodiesel or biofuel. Biodiesel ratio, which is 400 ml of cooking oil: 100 ml of methanol: 2.8 g of potassium hydroxide (KOH), is used in transesterification process. The ratio is used to reduce alcohol consumption and cost. Almost 97% of biodiesel are yielded by using this ratio with direct heating from hot magnetic stirrer. The Fourier Transform Infrared Spectroscopy (FTIR) results determine the biodiesels illustrate the exhibition of C=O and C-O, which is the functional groups of esters, whereas the conventional diesel fuel does not have any of the functional groups. In gas emission testing, the biodiesel blends are burned in ceramic beaker including B20, B60 and B100. NOx formation increases when the percentage for biodiesel blends are increase. In ThermaCAM P65 inspection, the testing shows that the temperature is directly proportional with the percentage of biodiesel blends. COME produced the highest amount of NOx than POME and PBDF; POME is the suitable alternative biodiesel fuel that can be used for Compression Ignition engine beside PBDF. The analysis is useful for researchers who intend to reduce NOx emission and improve air cleanliness by determining parameters and factors that can influence NOx formation

Charge-based compact model of gate-all-around floating gate nanowire with variable oxide thickness for flash memory cell

Due to high gate electrostatic control and introduction of punch and plug process technology, the gate-all-around (GAA) transistor is very promising in, and apparently has been utilized for, flash memory applications. However, GAA Floating Gate (GAA-FG) memory cell still requires high programming voltage that may be susceptible to cell-to-cell interference. Scaling down the tunnel oxide can reduce the Program/Erase (P/E) voltage but degrades the data retention capability. By using Technology-Computer-Aided-Design (TCAD) tools, the concept of tunnel barrier engineering using Variable Oxide Thickness (VARIOT) of low-k/high-k stack is utilized in compensating the trade-off between P/E operation and retention characteristics. Four high-k dielectrics (Si3N4, Al2O3, HfO2 and ZrO2) that are commonly used in semiconductor process technology are examined with SiO2 as its low-k dielectric. It is found that by using SiO2/Al2O3 as the tunnel layer, both the P/E and retention characteristics of GAA-FG can be compensated. About 30% improvement in memory window than conventional SiO2 is obtained and only 1% of charge-loss is predicted after 10 years of applying gate stress of -3.6V. Compact model of GAA-FG is initiated by developing a continuous explicit core model of GAA transistor (GAA Nanowire MOSFET (GAANWFET) and Juntionless Nanowire Transitor (JNT)). The validity of the theory and compact model is identified based on sophisticated numerical TCAD simulator for under 10% maximum error of surface potential. It is revealed that with the inclusion of partial-depletion conduction, the accuracy of the core model for GAANWFET is improved by more than 50% in the subthreshold region with doping-geometry ratio can be as high as about 0.86. As for JNT, despite the model being accurate for doping-geometry ratio upto 0.6, it is also independent of fitting parameters that may vary under different terminal biases or doping-geometry cases. The compact model of GAA-FG is completed by incorperating Charge Balance Model (CBM) into GAA transistor core model where good agreement is obtained with TCAD simulation and published experimental work. The CBM gives better accuracy than the conventional capacitive coupling approach under subthreshold region with approximately 10% error of floating gate potential. Therefore, the proposed compact model can be used to assist experimental work in extracting experimental data

Wireless power strip socket

Today, the demand on the electricity consumption is increasing throughout the society. Unfortunately, it goes without saying that in spite of the heavy consumption of the electricity, the number of damages and fatal accidents also caused by electricity if consumers neglected the safety precaution related to it. In fact, based on the statistics of the electrical accident released by the Energy Commission (ST), 13 cases of electric accidents occurred nationwide with seven involving the deceased in 2015 [1]. Researchers have taken the opportunities to invent many kinds of products or mechanism to minimize the losses created by the malfunctioning of the electrical devices. Having thought of the situation, a portable device using smartphones has been designed to encounter this matter

Geological Terrain Mapping using Geographic Information System (GIS) and Drone Photogrammetry

The research area was conducted within the Bukit Persekutuan, Kuala Lumpur, and it was located at the latitude 3° 8'32.93"N and longitude 101°40'32.80"E. The researcher carried out geological terrain mapping to evaluate the research area in accordance with the geological terrain classification attributes of each thematic map produced, namely, Terrain map, slope gradient map, erosion, and instability map, as well as construction suitability map. The occurrence of landslide events within the research area becomes a major contributing factor to thoroughly conducting an investigation by field mapping and analysing using the Geographic Information System (GIS) technology. The application of Geographic Information System (GIS) and drone photogrammetry images play an essential role to analyze and processing the data, thus, generate the thematic maps. The research area indicates that about 79.11% of the overall area was not appreciable with erosion, 8.58% contribute to the erosion, 11.00% of recent general instability and 2.97% represent a landslide event. The suitability for development mapping illustrated Class I (23.40), Class II (36.37%), Class III (26.39%), and Class IV (15.50%) where it can be referred to the construction suitability classification system, the suitability for development was high in class I, moderate in class II, low in class III and not suitable in class IV

Low-Power And High Performance Of An Optimized FinFET Based 8T SRAM Cell Design

The development of the nanotechnology leadsto the shrinking of the size of the transistors to nanometerregion. However, there are a lot of challenges due to sizescaling of the transistors such as short channel effects (SCEs)and threshold voltage roll-off issues. Fin-Type Field EffectTransistor (FinFET) is another alternative technology tosolve the issues of the conventional MOSFET and increasethe performance of the Static Random Access Memory(SRAM) circuit design. FinFET based SRAMs are faster andmore reliable which are often used as memory cache for highspeed operation. However, 6T SRAM cell suffers from accesstransistor sizing conflict resulting in a trade-off between readand write stability. This paper presents an investigation ofthe stability performance in retention, read and write modeof 22nm FinFET based 8T SRAM cell. The performancecomparison of 22nm FinFET based 6T and 8T SRAMs weremade. The simulation of the SRAM model are carried out inGTS Framework TCAD tool based on 22nm technology. In8T SRAM cell, two n-FinFETs are added to the conventional6T SRAM cell which will be controlled by the Read WordLine (RWL) to isolate the read and write operation path forbetter read stability. FinFET based 8T SRAM cell givesbetter performance in Static Noise Margin (SNM) and powerconsumption than 6T SRAM cells. The simulation resultsaffirms the proposed FinFET based 8T SRAM improvedread static noise margin by 166.67% and power consumptionby 76.13% as compared to the FinFET based 6T SRAM

Temperature Variation Operation of Mixed-VT 3T GC-eDRAM for Low Power Applications in 2Kbit Memory Array

Embedded memories were once utilized to transfer information between the CPU and the main memory. The cache storage in most traditional computers was static-random-access-memory (SRAM). Other memory technologies, such as embedded dynamic random-access memory (eDRAM) and spin-transfer-torque random-access memory (STT-RAM), have also been used to store cache data. The SRAM, on the other hand, has a low density and severe leakage issues, and the STT-RAM has high latency and energy consumption when writing. The gain-cell eDRAM (GC-eDRAM), which has a higher density, lower leakage, logic compatibility, and is appropriate for two-port operations, is an attractive option. To speed up data retrieval from the main memory, future processors will require larger and faster-embedded memories. Area overhead, power overhead, and speed performance are all issues with the existing architecture. A unique mixed-V_T 3T GC-eDRAM architecture is suggested in this paper to improve data retention times (DRT) and performance for better energy efficiency in embedded memories. The GC-eDRAM is simulated using a standard complementary-metal-oxide-semiconductor (CMOS) with a 130nm technology node transistor. The performance of a 2kbit mixed-V_T 3T GC-eDRAM array were evaluated through corner process simulations. Each memory block is designed and simulated using Mentor Graphics Software. The array, which is based on the suggested bit-cell, has been successfully operated at 400Mhz under a 1V supply and takes up almost 60-75% less space than 6T SRAM using the same technology. When compared to the existing 6T and 4T ULP SRAMs (others' work), the retention power of the proposed GC-eDRAM is around 80-90% lower

Impact of Device Parameter Variation on the Electrical Characteristic of N-type Junctionless Nanowire Transistor with High-k Dielectrics

Metallurgical junction and thermal budget are serious constraints in scaling and performance of conventional metal-oxide-semiconductor field-effect transistor (MOSFET). To overcome this problem, junctionless nanowire field-effect transistor (JLNWFET) was introduced. In this paper, we investigate the impact of device parameter variation on the performance of n-type JLNWFET with high-k dielectrics. The electrical characteristic of JLNWFET and the inversion-mode transistor of different gate length (LG) and nanowire diameter (dNW) was compared and analyzed. Different high-k dielectrics were used to get an optimum device structure of JLNWFET. The device was simulated using SDE Tool of Sentaurus TCAD and the I-V characteristics were simulated using Sdevice Tools. Lombardi mobility model and Philips unified mobility model were applied to define its electric field and doping dependent mobility degradation. A thin-film heavily doped silicon nanowire with a gate electrode that controls the flow of current between the source and drain was used. The proposed JLNWFET exhibits high ON-state current (ION) due to the high doping concentration (ND) of 1 x 1019 cm-3 which leads to the improved ON-state to OFF-state current ratio (ION/IOFF) of about 10% than the inversion-mode device for a LG of 7 nm and the silicon dNW of 6 nm. Electrical characteristics such are drain induced barrier lowering (DIBL) and subthreshold slope (SS) were extracted which leads to low leakage current as well as a high ION/IOFF ratio. The performance was improved by introducing silicon dioxide (SiO2) with high-k dielectric materials, hafnium oxide (HfO2) and silicon nitrate (Si3N4). It was found that JLNWFET with HfO2 exhibits better electrical characteristics and performance

Reliability of graphene as charge storage layer in floating gate flash memory

This study aims to investigate the memory performances of graphene as a charge storage layer in the floating gate with difference doping concentration of n-channel and p-channel substrates using Silvaco ATLAS TCAD Tools. The simulation work has been done to determine the performance of flash memory in terms of memory window, P/E characteristics and data retention and have been validated with the experimental work done by other researchers. From the simulation data, the trend of memory window at low P/E voltage is nearly overlapped between simulation and experimental data. The memory window at ±20V P/E voltage for n-channel and p-channel flash memory cell are 15.4V and 15.6V respectively. The data retention for the n-channel flash memory cell is retained by 75% (from 15.4V to 11.6V) whereas for the p-channel flash memory cell is retained by 80% (from 15.6V to 12.5V) after 10 years of extrapolation with -1/1V gate stress which shows that p-channel flash memory cell demonstrates better data retention compared to n-channel flash memory cell

Analytical prediction of highly sensitive CNT-FET-based sensor performance for detection of gas molecule

In this study, a set of new analytical models to predict and investigate the impacts of gas adsorption on the electronic band structure and electrical transport properties of the single-wall carbon nanotube field-effect transistor (SWCNT-FET) based gas sensor are proposed. The sensing mechanism is based on introducing new hopping energy and on-site energy parameters for gas-carbon interactions representing the charge transfer between gas molecules (CO2, NH3, and H2O) and the hopping energies between carbon atoms of the CNT and gas molecule. The modeling starts from the atomic level to the device level using the tight-binding technique to formulate molecular adsorption effects on the energy band structure, density of states, carrier velocity, and I-V characteristics. Therefore, the variation of the energy bandgap, density of states and current-voltage properties of the CNT sensor in the presence of the gas molecules is discovered and discussed. The simulated results show that the proposed analytical models can be used with an electrical CNT gas sensor to predict the behavior of sensing mechanisms in gas sensors

Influence of single vacancy defect at varying length on electronic properties of zigzag graphene nanoribbons

Graphene, identified in 2004, is now an established two-dimensional (2D) material due to its outstanding physical and electronic characteristics namely its superior electrical conductivity. Graphene is a zero-gap material that has linear dispersion with electron-hole symmetry. As pristine sheet, it cannot be utilized in digital logic application without the induction of a band gap inside the band structure. In our work, the modeling and simulation of graphene nanoribbons (GNRs) are carried out to determine its electronics properties that are benchmarked with other published simulation data. A 4-Zigzag GNRs (4-ZGNRs) under different length are utilized. A single vacancy defects is introduced at various positions inside the atomic structure. The theoretical model is implemented based on single-neighbour tight binding technique coupled with a non-equilibrium Green’s function formalism. The single vacancy defects are represented by the elimination of tight binding energies in the Hamiltonian matrix. Subsequently, these matrix elements are utilized to compute dispersion relation and density of states (DOS) through Green’s function. It is found that single vacancy defects at different positions in 4-ZGNRs’ atomic structure under varying length has no significant impacts on the sub-band structure but these vacancies impact the DOS that are computed throught Green’s function approach